12 Gbit/s three‐tap FFE half‐rate transmitter with low jitter clock buffering scheme. Issue 20 (1st October 2019)

• Record Type: Journal Article
• Authors: Park, K.; Oh, T.
• Is Part Of: Electronics letters. Volume 55:Issue 20(2019)
• Page Start: 1078
• Page End: 1080
• Publication Date: 2019-10-01
• Subjects: equalisers -- transmitters -- error statistics -- CMOS integrated circuits -- clocks -- jitter -- buffer circuits -- feedforward -- integrated circuit design; three‐tap FFE half‐rate transmitter -- low jitter clock buffering scheme -- segmented FFE driver -- equivalent signal transition -- segmented unit -- low jitter performance -- RMS jitter -- prototype transmitter -- feedforward equalisation transmitter -- CMOS process -- three‐tap high‐speed tap signal generation technique -- half‐rate high‐speed tap signal generation technique -- horizontal eye‐opening -- BER -- bit rate 12.0 Gbit/s -- size 65.0 nm -- time 9.31 ps; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2019.2226
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A 12 Gbit/s feed‐forward equalisation (FFE) transmitter has been designed in 65 nm CMOS process. The three‐tap/half‐rate high‐speed tap signal generation technique for the segmented FFE driver is presented. A clock buffer scheme to make the equivalent signal transition for each segmented unit contributes to a low jitter performance. The measurement results show 9.31 ps RMS jitter at 12 Gbit/s after equalisation and the horizontal eye‐opening is 0.204 UI at 10 − 12 BER. The prototype transmitter occupies 0.042 m m 2 and consumes 1.58 pJ/bit.