Carrier‐storage‐enhanced superjunction IGBT with n‐Si and p‐3C‐SiC pillars. Issue 25 (1st December 2019) - Li, Rui; Huang, Mingmin; Yang, Zhimei; Ma, Yao; Gong, Min
Abstract : A carrier‐storage‐enhanced superjunction (SJ) insulated gate bipolar transistor (IGBT) with n‐Si and p‐3C‐SiC pillars (Si/SiC SJ IGBT) is studied. At the on‐state, the n‐Si/p‐SiC heterojunction acts as a barrier for holes in the n‐Si pillar, which helps to enhance the carrier‐storage effect in the n‐Si pillar and improves the tradeoff between turn‐off loss ( E off ) and on‐state voltage drop ( V CE(sat) ). It is found by simulations that V CE(sat) of the Si/SiC SJ IGBT can be 0.35 V lower than that of the conventional SJ IGBT with the same breakdown voltage ( V B = 1450 V). Under E off = 5 mJ/cm 2, V CE(sat) of the Si/SiC SJ IGBT is 1.22 V, which is 0.30 and 0.81 V lower than V CE(sat) of the conventional SJ IGBT and the field stop IGBT, respectively.