Stretched tunnelling body contact structure for suppressing the FBE in a vertical cell DRAM. Issue 23 (1st November 2019)

• Record Type: Journal Article
• Authors: Cho, Y.S.; Choi, P.H.; Kim, K.H.; Park, J.M.; Hwang, Y.S.; Hong, H.S.; Lee, K.P.; Choi, B.D.
• Is Part Of: Electronics letters. Volume 55:Issue 23(2019)
• Page Start: 1252
• Page End: 1253
• Publication Date: 2019-11-01
• Subjects: DRAM chips -- tunnel diodes -- flexible electronics -- transistor circuits; vertical cell transistor -- dynamic random access memory -- stretched tunnelling diode -- buried body -- stretched tunnelling body contact structure -- vertical cell DRAM -- FBE -- OFF‐state current -- floating body effect -- n+ active layer -- p+ layer; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2019.2541
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Vertical cell transistor is necessary to drastically reduce the chip size of the dynamic random access memory. This structure has a great advantage in terms of shrinkage, but it also has the disadvantage of increasing the OFF‐state current by causing floating body effect (FBE). For the first time, it is demonstrated that a stretched tunnelling diode, which consists of a p + layer next to the n + active layer in the buried body, leads to a drastically suppressed FBE. The OFF‐state current is sharply reduced by about seven orders compared with a conventional structure. Furthermore, the decrease in the OFF‐state current is at minimum when the length of the stretched p + region is approximately half the channel length ( L p / L =1/2).