Current adjustable clock distribution network scheme for GDDR5. Issue 11 (1st May 2013)
- Record Type:
- Journal Article
- Title:
- Current adjustable clock distribution network scheme for GDDR5. Issue 11 (1st May 2013)
- Main Title:
- Current adjustable clock distribution network scheme for GDDR5
- Authors:
- Lim, S.‐B.
Hwang, S.
You, J.
Baek, Y.
Kim, C. - Abstract:
- Abstract : Presented is a current adjustable clock distribution network for GDDR5. In general, GDDR5 uses a current mode logic (CML) buffer as the global driver of the clock distribution. The wide‐frequency range conventional CML buffer is designed to the fastest frequency. However, the CML buffer consumes constant current at all frequencies. For this reason, the conventional buffer dissipates current more than necessary at low frequencies. A proposed current adjustable clock distribution network scheme adjusts the amount of the current consumption of the global driver according to the clock frequency. The proposed scheme is implemented in 65 nm CMOS technology, reduces power consumption by 17.7% in the wide frequency range from an average 10.26 mW of the conventional scheme to 8.44 mW.
- Is Part Of:
- Electronics letters. Volume 49:Issue 11(2013)
- Journal:
- Electronics letters
- Issue:
- Volume 49:Issue 11(2013)
- Issue Display:
- Volume 49, Issue 11 (2013)
- Year:
- 2013
- Volume:
- 49
- Issue:
- 11
- Issue Sort Value:
- 2013-0049-0011-0000
- Page Start:
- 689
- Page End:
- 691
- Publication Date:
- 2013-05-01
- Subjects:
- buffer circuits -- CMOS logic circuits -- current distribution -- current‐mode logic -- driver circuits -- clock distribution networks
current adjustable clock distribution network scheme -- GDDR5 -- current mode logic buffer -- wide‐frequency range -- CML buffer -- conventional buffer current dissipation -- constant current consumption -- global driver -- CMOS technology -- clock frequency -- size 65 nm -- power 10.26 mW
buffer circuits -- CMOS logic circuits -- current distribution -- current‐mode logic -- driver circuits -- clock distribution networks
current adjustable clock distribution network scheme -- GDDR5 -- current mode logic buffer -- wide‐frequency range -- CML buffer -- conventional buffer current dissipation -- constant current consumption -- global driver -- CMOS technology -- clock frequency -- size 65 nm -- power 10.26 mW
Electronics -- Periodicals
621.381 - Journal URLs:
- http://digital-library.theiet.org/content/journals/el ↗
http://estar.bl.uk/cgi-bin/sciserv.pl?collection=journals&journal=00135194 ↗
https://ietresearch.onlinelibrary.wiley.com/loi/1350911x ↗
http://www.theiet.org/ ↗ - DOI:
- 10.1049/el.2012.3859 ↗
- Languages:
- English
- ISSNs:
- 0013-5194
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 3705.060000
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 16457.xml