0.8‐V 1.4‐nW multi‐decade frequency range true RMS to DC converter based on two‐quadrant current squarer circuit. Issue 1 (1st January 2020)

• Record Type: Journal Article
• Authors: Maryan, Mohammad Moradinezhad; Azhari, Seyed Javad; Ayatollahi, Ahmad; Sajadinia, Hamed
• Is Part Of: IET science, measurement & technology. Volume 14:Issue 1(2020)
• Page Start: 17
• Page End: 25
• Publication Date: 2020-01-01
• Subjects: integrated circuit design -- CMOS integrated circuits -- low‐power electronics -- Monte Carlo methods -- frequency convertors; TSMC CMOS process -- two‐quadrant current squarer circuit -- low‐voltage ultra‐low‐power two‐quadrant current squarer based‐true RMS -- DC converter circuit -- matched NMOS transistors -- ultra‐low‐power dissipation -- multidecade frequency range true RMS to DC converter circuits -- translinear loops -- post‐layout simulations -- HSPICE software -- Monte Carlo analysis -- PVT robustness -- design performance reliability -- power 1.4 nW -- size 0.18 mum -- frequency 0.5 Hz to 55.0 kHz -- voltage 0.8 V -- current 72 nA to 1 nA -- V; Measurement -- Periodicals; Electrical engineering -- Periodicals; Electronics -- Periodicals; Nanotechnology -- Periodicals; Electromagnetism -- Periodicals; Medical instruments and apparatus -- Periodicals; 621.3
• DOI: 10.1049/iet-smt.2019.0007
• Languages: English
• ISSNs: 1751-8822

Abstract

Abstract : A low‐voltage ultra‐low‐power two‐quadrant current squarer based‐true RMS to DC converter circuit is presented in this study. The proposed current squarer is based on two translinear loops with matched NMOS transistors operating in the weak inversion region. Ultra‐low‐power dissipation of 1.4 nW, multi‐decade frequency range of 0.5 Hz–55 kHz and large input dynamic range of 72 pA–1 nA (with error <3%) are the main achievements of the proposed design while constructed of only ten transistors. Post‐layout simulations with 0.8‐V supply voltage using HSPICE software in 0.18 μm TSMC CMOS process (level‐49 parameters) verified the good functionality of the proposed circuit. Moreover, Monte Carlo analysis is performed to validate the satisfactory PVT robustness and reliability of the design's performance.