Low power 2D finite impulse response filter design using modified artificial bee colony algorithm with experimental validation using field‐programmable gate array. Issue 6 (1st September 2016)

• Record Type: Journal Article
• Authors: Dwivedi, Atul Kumar; Ghosh, Subhojit; Londhe, Narendra D.
• Is Part Of: IET science, measurement & technology. Volume 10:Issue 6(2016)
• Page Start: 671
• Page End: 678
• Publication Date: 2016-09-01
• Subjects: FIR filters -- field programmable gate arrays -- singular value decomposition -- band‐pass filters -- band‐stop filters -- minimisation; low power 2D finite impulse response filter design -- modified artificial bee colony algorithm -- field‐programmable gate array -- cooling -- maintenance -- power consumption -- PC -- low power two‐dimensional FIR filter -- singular value decomposition -- Hamming distance -- optimisation problem -- circular shaped 2D FIR filter -- frequency domain analysis -- pass band ripple minimisation -- stop band ripple minimisation -- Xilinx X‐power analyser; Measurement -- Periodicals; Electrical engineering -- Periodicals; Electronics -- Periodicals; Nanotechnology -- Periodicals; Electromagnetism -- Periodicals; Medical instruments and apparatus -- Periodicals; 621.3
• DOI: 10.1049/iet-smt.2016.0069
• Languages: English
• ISSNs: 1751-8822

Abstract

Abstract : Motivated by the need of reducing power consumption (PC) in two dimensional (2D) finite impulse response (FIR) filters, in this work, the 2D FIR filter design task is formulated as an optimisation problem that seeks to attain the desired frequency response and reduces PC. The optimisation problem has been solved using the modified version of artificial bee colony algorithm. The applicability of the proposed approach has been evaluated by designing circular shaped 2D FIR filters for a set of specifications in frequency domain. The designed filters have been compared with other reported state of the art techniques. The evaluation is carried out in terms of pass band and stop band ripple minimisation, convergence profile and PC during filter execution in hardware. The proposed technique is found to outperform all other techniques in achieving minimum ripple for a given filter order. To prove the effectiveness of the proposed approach for PC reduction, the designed filters have been implemented in hardware using field‐programmable gate array (xc7vx485t‐2ffg1761). The PC computed using Xilinx X‐power analyser shows that 23.53% power can be saved using the proposed approach as compared with conventional design approaches.