Chaos assisted variable bit steganography in transform domain. Issue 23 (1st November 2018)

• Record Type: Journal Article
• Authors: Dhivya, R.; Padmapriya, V.; Sundararaman, R.; Rayappan, J.B.B.; Amirtharajan, R.
• Is Part Of: Electronics letters. Volume 54:Issue 23(2018)
• Page Start: 1332
• Page End: 1334
• Publication Date: 2018-11-01
• Subjects: steganography -- chaos -- wavelet transforms -- data encapsulation; CCS -- IWT -- integer wavelet transform -- chaos assisted variable bit steganography -- variable bit data hiding scheme -- security level maximization -- 1D chaotic maps -- combined sine‐tent maps -- CTL maps -- combined tent‐logistic maps -- combined sine‐logistic maps -- CST maps -- CSL maps -- chaotic key sequence generation -- improved combined chaotic system; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2018.6426
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An efficient variable bit data hiding scheme based on combined chaotic system (CCS) and integer wavelet transform (IWT) is proposed. With the aim to maximise the security level, CCS is developed by combining two 1D chaotic maps. The developed combined tent‐logistic (CTL), combined sine‐logistic (CSL) and combined sine‐tent (CST) maps with improved chaotic behaviour are utilised to generate the key sequences. These chaotic key sequences from CTL, CSL and CST are then quantised to embed the secret bits in high‐high, high‐low and low‐high sub‐bands of the IWT transformed cover image, respectively. The main advantage of this scheme is that the number of bits to be embedded in each and every sub‐band coefficients is highly chaotic and extremely sensitive to the initial seeds.