Software tool for efficient FPGA design of direct data domain approach for space‐time adaptive processing. Issue 13 (1st June 2013)

• Record Type: Journal Article
• Authors: Jarrah, A.; Jamali, M.
• Is Part Of: Electronics letters. Volume 49:Issue 13(2013)
• Page Start: 789
• Page End: 791
• Publication Date: 2013-06-01
• Subjects: electronic engineering computing -- field programmable gate arrays -- hardware description languages -- interference suppression -- logic design -- space‐time adaptive processing -- system‐on‐chip; software tool -- FPGA design -- direct data domain approach -- space‐time adaptive processing algorithms -- fast‐changing clutter scenario -- data stationary property -- interference scenario -- fully optimissed VHDL representation -- system on chip -- SoC -- D3 algorithm; electronic engineering computing -- field programmable gate arrays -- hardware description languages -- interference suppression -- logic design -- space‐time adaptive processing -- system‐on‐chip; software tool -- FPGA design -- direct data domain approach -- space‐time adaptive processing algorithms -- fast‐changing clutter scenario -- data stationary property -- interference scenario -- fully optimissed VHDL representation -- system on chip -- SoC -- D3 algorithm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.1307
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Space‐time adaptive processing algorithms have been proven to be a very effective way to mitigate the effects of multipath and interference. Due to the fast‐changing clutter scenario, the stationary property of the data is destroyed and fails if the interference scenario ever becomes heterogeneous. Direct data domain (D 3 ) methods can accommodate non‐stationary data and can effectively suppress the clutter. However, the computation of D 3 is very intensive. It is desirable to implement the D 3 algorithm on a FPGA architecture for real‐time applications. FPGAs can accommodate parallel and pipelined architecture. Here, the first FPGA design for the D 3 algorithm and a new software package are presented. The software tool is capable of auto‐generating a fully optimised VHDL representation of D 3 and provides various performance parameters. The tool can be used by the designer to develop an overall system on chip (SoC) by using various constraints and options to meet certain performance criteria. Experimental results demonstrate that the authors' hardware version of the D 3 algorithm can significantly outperform an equivalent software version.