Multi‐FPGA digital hardware design for detailed large‐scale real‐time electromagnetic transient simulation of power systems. Issue 5 (1st May 2013)

• Record Type: Journal Article
• Authors: Chen, Yuan; Dinavahi, Venkata
• Is Part Of: IET generation, transmission & distribution. Volume 7:Issue 5(2013)
• Page Start: 451
• Page End: 463
• Publication Date: 2013-05-01
• Subjects: field programmable gate arrays -- iterative methods -- power system simulation; multiFPGA digital hardware design -- detailed large‐scale real‐time electromagnetic transient simulation -- power systems -- detailed modelling -- functional decomposition method -- FPGA hardware resources -- system modelling -- fully‐pipelined‐parallel hardware emulation -- component model -- 3‐FPGA real‐time hardware emulation -- 10‐FPGA real‐time hardware emulation -- three‐phase 42‐bus power systems -- three‐phase 420‐bus power systems -- iterative nonlinear solution -- FPGA clock -- offline simulation result -- frequency 100 MHz; Electric power production -- Periodicals; Electric power transmission -- Periodicals; Electric power distribution -- Periodicals; 621.3105
• DOI: 10.1049/iet-gtd.2012.0374
• Languages: English
• ISSNs: 1751-8687

Abstract

Abstract : Large‐scale electromagnetic transient simulation of power systems in real‐time using detailed modelling is computationally very demanding. This study introduces a multi‐field programmable gate array (FPGA) hardware design for this purpose. A functional decomposition method is proposed to map FPGA hardware resources to system modelling. This systematic method lends itself to fully pipelined and parallel hardware emulation of individual component models and numerical solvers, while preserving original system characteristics without the need for extraneous components to partition the system. Proof‐of‐concept is provided in terms of a 3‐FPGA and 10‐FPGA real‐time hardware emulation of a three‐phase 42‐bus and 420‐bus power systems using detailed modelling of various system components and iterative non‐linear solution on a 100 MHz FPGA clock. Real‐time results are compared with offline simulation results, and conclusions are derived on the performance and scalability of this multi‐FPGA hardware design.