0.0045 mm2 15.8 µW three‐stage amplifier driving 10×‐wide (0.15–1.5 nF) capacitive loads with >50° phase margin. Issue 6 (1st March 2015)

• Record Type: Journal Article
• Authors: Yan, Zushu; Mak, Pui‐In; Law, Man‐Kay; Martins, Rui Paulo
• Is Part Of: Electronics letters. Volume 51:Issue 6(2015)
• Page Start: 454
• Page End: 456
• Publication Date: 2015-03-01
• Subjects: amplifiers -- CMOS analogue integrated circuits; embedded capacitor‐multiplier compensation -- ECMC -- active parallel compensation -- APC -- area efficiency enhancement -- nF‐range capacitive loads -- dominant compensation path -- large gain‐bandwidth product -- left‐half‐plane zero -- phase margin -- PM -- passive parallel compensation -- Miller effect -- transconductance -- DC gain -- CMOS three‐stage amplifier -- figure‐of‐merit -- power 15.8 muW -- capacitance 0.15 nF to 1.5 nF -- size 0.18 mum -- frequency 1.13 MHz; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2014.4391
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A three‐stage amplifier employing embedded capacitor‐multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF‐range capacitive loads ( C L ) is presented. Unlike the conventional current‐buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left‐half‐plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area‐consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi‐path G m ‐boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm 2 of area and 15.8 µW of power, the 0.18 µm CMOS three‐stage amplifier measures 1.13 MHz unity‐gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L . Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure‐of‐merit accounting for both die area and power compares favourably with the state of the art.