High‐performance and single event double‐upset‐immune latch design. Issue 23 (6th October 2020)

• Record Type: Journal Article
• Authors: Zhang, Haineng; Liu, Zhongyang; Jiang, Jianwei; Xiao, Jun; Zhang, Zhengxuan; Zou, Shichang
• Is Part Of: Electronics letters. Volume 56:Issue 23(2020)
• Page Start: 1243
• Page End: 1245
• Publication Date: 2020-10-06
• Subjects: logic design -- flip‐flops -- CMOS integrated circuits -- MOSFET -- CMOS logic circuits -- radiation hardening (electronics); 84.56% area‐power‐delay product saving -- PMOS transistors -- NMOS transistors -- interlocked branch circuits -- single event double‐upset‐fully‐tolerant latch -- single event double‐upset‐immune latch design -- SEDU -- recently reported latches; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2020.1823
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : This Letter proposes a single event double‐upset (SEDU)‐fully‐tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area‐power‐delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.