Simplified drain current model for pinch‐off double gate junctionless transistor. Issue 2 (1st January 2014)

• Record Type: Journal Article
• Authors: Sahu, C.; Swami, P.; Sharma, S.; Singh, J.
• Is Part Of: Electronics letters. Volume 50:Issue 2(2014)
• Page Start: 116
• Page End: 118
• Publication Date: 2014-01-01
• Subjects: analogue circuits -- field effect transistors; TCAD simulation -- analogue circuits -- transconductance‐to‐drain‐current ratio -- device dimensions -- bias conditions -- gate capacitance -- pinch‐off voltage -- mobile charge density -- JL DGFET -- long‐channel pinch‐off junctionless double‐gate field effect transistor -- simplified analytical drain current model; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.3342
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A simplified analytical drain current model for the long‐channel pinch‐off junctionless (JL) double‐gate field effect transistor (DGFET) is proposed. The drain current is generally expressed in terms of the mobile charge density and it has been expressed in terms of the pinch‐off voltage and the gate capacitance. The proposed model is validated against TCAD simulation results, and is able to predict the behaviour of the JL DGFET for different bias conditions and device dimensions, accurately. The transconductance and the transconductance‐to‐drain‐current ratio are important parameters for analogue circuits, and have been calculated and exhibit good agreement with the TCAD results.