Vertical type double gate tunnelling FETs with thin tunnel barrier. Issue 9 (1st April 2015)

• Record Type: Journal Article
• Authors: Kim, Jang Hyun; Kim, Sang Wan; Kim, Hyun Woo; Park, Byung‐Gook
• Is Part Of: Electronics letters. Volume 51:Issue 9(2015)
• Page Start: 718
• Page End: 720
• Publication Date: 2015-04-01
• Subjects: field effect transistors -- tunnelling -- silicon -- elemental semiconductors; Si -- gradual doping -- capping layer -- threshold voltages -- tunnelling regions -- transfer curves -- hump phenomenon -- steep subthreshold swing -- L‐shaped TFET -- bulk Si substrate -- thin tunnel junction -- vertical type tunnelling field‐effect transistor -- thin tunnel barrier -- vertical type double gate tunnelling FET; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2014.3864
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A vertical type tunnelling field‐effect transistor (TFET) with a thin tunnel junction based on a bulk Si substrate is presented. In the authors' previously reported L‐shaped TFET, a thin tunnel barrier and a large tunnelling area were employed on the source side to achieve a steep subthreshold swing (SS) and high on‐current, which can lead to the TFET's outstanding performance. The proposed TFET devices demonstrate a SS of 32 mV/decade averaged over five decades and an I on > 10 −5 A/μm. Moreover, the on‐current can be increased easily by adjusting the height of the source. However, since a hump phenomenon in the transfer curves occurred, the hump behaviour in the proposed device was investigated. After investigating it, the hump behaviour was found to have originated from two different tunnelling regions. Moreover, their threshold voltages show different values. Using a capping layer that can be made by gradual doping, the hump behaviour can be suppressed.