Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing. Issue 19 (1st September 2016)
- Record Type:
- Journal Article
- Title:
- Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing. Issue 19 (1st September 2016)
- Main Title:
- Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing
- Authors:
- Labrado, C.
Thapliyal, H. - Abstract:
- Abstract : Implementation of a five‐input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library.
- Is Part Of:
- Electronics letters. Volume 52:Issue 19(2016)
- Journal:
- Electronics letters
- Issue:
- Volume 52:Issue 19(2016)
- Issue Display:
- Volume 52, Issue 19 (2016)
- Year:
- 2016
- Volume:
- 52
- Issue:
- 19
- Issue Sort Value:
- 2016-0052-0019-0000
- Page Start:
- 1618
- Page End:
- 1620
- Publication Date:
- 2016-09-01
- Subjects:
- logic design -- adders -- nanomagnetics -- magnetic logic
multilayer five‐input majority gate design -- adder‐subtractor circuits -- NML computing -- nanomagnetic logic -- special purpose Verilog library
Electronics -- Periodicals
621.381 - Journal URLs:
- http://digital-library.theiet.org/content/journals/el ↗
http://estar.bl.uk/cgi-bin/sciserv.pl?collection=journals&journal=00135194 ↗
https://ietresearch.onlinelibrary.wiley.com/loi/1350911x ↗
http://www.theiet.org/ ↗ - DOI:
- 10.1049/el.2016.2294 ↗
- Languages:
- English
- ISSNs:
- 0013-5194
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 3705.060000
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 16435.xml