Five to 25 Gb/s continuous time linear equaliser with transversal architecture. Issue 25 (1st December 2017)

• Record Type: Journal Article
• Authors: Zhang, H.; Monaco, E.; Bassi, M.; Mazzanti, A.
• Is Part Of: Electronics letters. Volume 53:Issue 25(2017)
• Page Start: 1629
• Page End: 1630
• Publication Date: 2017-12-01
• Subjects: equalisers -- mean square error methods -- gradient methods -- CMOS integrated circuits; continuous time linear equaliser -- transversal architecture -- transceiver -- backplane serial link -- CTLE -- paraboloid mean square‐error surface -- voltage 1 V -- power 17 mW -- loss 20 dB -- bit rate 5 Gbit/s to 25 Gbit/s -- size 28 nm -- BER -- CMOS technology -- gradient descent algorithm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2017.3120
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with high accuracy in matching the channel response. A continuous time linear equaliser (CTLE) with a transversal architecture features variable DC gain and two zeros that can be tuned independently. The transversal architecture yields a paraboloid mean‐square‐error surface, allowing optimal adaptation through gradient descent algorithms. The CTLE was realised in a 28 nm CMOS technology and measurements are presented at data rate from 5 to 25 Gb/s across 20 dB‐loss channels. Core power dissipation is 17 mW from 1 V supply and horizontal eye opening at BER 10 −12 is equal or larger than 50%, comparing favourably against previously reported equalisers targeting similar data‐rate and channel loss.