Parallel array histogram architecture for embedded implementations. Issue 2 (1st January 2013)

• Record Type: Journal Article
• Authors: Gan, Q.; Langlois, J.M.P.; Savaria, Y.
• Is Part Of: Electronics letters. Volume 49:Issue 2(2013)
• Page Start: 99
• Page End: 101
• Publication Date: 2013-01-01
• Subjects: embedded systems -- microprocessor chips -- parallel architectures; parallel array histogram architecture -- embedded implementation -- PAHA -- register array -- histogram bins -- general‐purpose processor; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2012.2701
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Proposed is a parallel array histogram architecture (PAHA) suitable for embedded implementations. The PAHA uses a register array instead of a memory block to store the histogram bins. In each step, M inputs can be processed in parallel to update the histogram bins without any additional latency. Also described is a second version of the PAHA with a flexible number of inputs, potentially avoiding the need for multiple PAHAs in a single application. Implementation results show that the architecture can achieve a super‐linear speed‐up of 43.75× for a 16‐way PAHA when compared to a software implementation in a general‐purpose processor.