Digital background calibration technique for pipelined SAR ADCs with detect‐and‐switching algorithm. Issue 11 (1st May 2020)

• Record Type: Journal Article
• Authors: Zhang, Lizhen; Han, Shanshan; Huang, Linlin; Wu, Jianhui
• Is Part Of: Electronics letters. Volume 56:Issue 11(2020)
• Page Start: 533
• Page End: 536
• Publication Date: 2020-05-01
• Subjects: calibration -- analogue‐digital conversion -- combinational circuits; pipelined SAR ADC -- inter‐stage gain -- DAS‐based calibration -- first‐stage residue voltage -- capacitor mismatch -- injected dithering signal -- random dithering signal -- combinational logic -- DAS algorithm -- detect‐and‐switching algorithm -- analogue‐to‐digital converters -- digital background calibration technique; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2020.0320
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A digital background calibration technique for pipelined successive approximation register (SAR) analogue‐to‐digital converters (ADCs) with detect‐and‐switching (DAS) algorithm is proposed. The DAS algorithm exploits basic combinational logic to detect the first‐stage conversion results, thereby determining whether to inject a random dithering signal. So as to reduce the amplifier's output swing and avoid the saturation of the second stage, the amplitude of the injected dithering signal is reduced by only injecting the capacitor mismatch into first‐stage residue voltage. By executing the DAS‐based calibration in the background, capacitor mismatch and inter‐stage gain are obtained. Simulation results show that the signal to noise and distortion ratio is improved from 42.4 to 59.3 dB and spurious‐free dynamic range is increased from 50.6 to 79.1 dB with calibration.