Low‐power charge‐steering phase interpolator. Issue 10 (1st May 2016)

• Record Type: Journal Article
• Authors: Elnaqib, A.; Ibrahim, S.A.
• Is Part Of: Electronics letters. Volume 52:Issue 10(2016)
• Page Start: 810
• Page End: 812
• Publication Date: 2016-05-01
• Subjects: CMOS integrated circuits -- clock and data recovery circuits -- phase locked loops -- low‐power electronics; frequency 5 GHz -- voltage 1 V -- power 180 muW -- word length 6 bit -- size 65 nm -- CMOS technology -- charge‐based phase interpolator -- clock and data recovery circuits -- phase‐locked loop -- low‐power charge‐steering phase interpolator; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.3968
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : The demand for low‐power equalisation at high data rates in serial‐link receivers has prioritised the issue of power consumption. This high demand has also involved the phase‐locked loop (PLL) and clock and data recovery (CDR) circuits. This propelled efforts to further optimise the PLLs and CDRs building blocks and to pursue low‐power solutions. A charge‐based phase interpolator (PI) is presented. It employs charge‐steering circuits in order to reduce the power typically consumed by its current‐based counterpart. Implemented in 65‐nm CMOS technology, a 6‐bit charge‐based PI consumes 180 μW at 1–V supply and 5‐GHz clock.