2 × 3.2 Gb/s single‐ended IO transmitter with low‐power dynamic FIR driver for the LPDDR4 standard. Issue 24 (1st November 2017)

• Record Type: Journal Article
• Authors: Kim, S.; Oh, T.
• Is Part Of: Electronics letters. Volume 53:Issue 24(2017)
• Page Start: 1566
• Page End: 1568
• Publication Date: 2017-11-01
• Subjects: CMOS integrated circuits -- radio transmitters -- low‐power electronics -- driver circuits; single‐ended IO transmitter -- low‐power dynamic FIR driver -- LPDDR4 standard -- low‐power double‐data rate 4 standard -- prototype transmitter architecture -- CMOS process -- pre‐emphasis tap weighting -- size 45 nm -- power 2.25 mW -- bit rate 3.2 Gbit/s; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2017.2768
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A novel FIR driver that can be applied to a low power mode in the (Low Power Double Data Rate 4) LPDDR4 standard has been developed. The proto‐type transmitter architecture is implemented in 45 nm CMOS process and occupies 0.009 mm 2 area. The pre‐emphasis tap weighting improves the eye opening by 27.9% vertically and 27% horizontally, respectively, and the transmitter consumes only 2.25 mW at 3.2 Gb/s.