Ultra‐low‐power adaptable ASK clock and data recovery circuit for wireless implantable systems. Issue 10 (1st May 2013)

• Record Type: Journal Article
• Authors: Yu, H.; Li, Y.; Jiang, L.; Ji, Z.
• Is Part Of: Electronics letters. Volume 49:Issue 10(2013)
• Page Start: 638
• Page End: 639
• Publication Date: 2013-05-01
• Subjects: amplifiers -- amplitude shift keying -- biomedical electronics -- CMOS integrated circuits -- demodulation -- low‐power electronics -- prosthetics -- pulse position modulation -- recorders -- clock and data recovery circuits; ultralow power adaptable ASK clock -- amplitude shift keying -- pulse position modulation -- self‐synchronised data recovery circuit -- wireless implantable neural recoding system -- ultralow power clock and data recovery circuit -- CDR -- gain‐boosted front‐end amplifier -- inductive load -- charge‐bump based circuit -- nonreturn‐to‐zero data -- NRZ -- PPM signal demodulation -- standard CMOS process -- frequency 1 MHz -- size 0.25 mum -- bit rate 19 kbit/s to 76 kbit/s; amplifiers -- amplitude shift keying -- biomedical electronics -- CMOS integrated circuits -- demodulation -- low‐power electronics -- prosthetics -- pulse position modulation -- recorders -- clock and data recovery circuits; ultralow power adaptable ASK clock -- amplitude shift keying -- pulse position modulation -- self‐synchronised data recovery circuit -- wireless implantable neural recoding system -- ultralow power clock and data recovery circuit -- CDR -- gain‐boosted front‐end amplifier -- inductive load -- charge‐bump based circuit -- nonreturn‐to‐zero data -- NRZ -- PPM signal demodulation -- standard CMOS process -- frequency 1 MHz -- size 0.25 mum -- bit rate 19 kbit/s to 76 kbit/s; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.0844
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Amplitude shift keying (ASK) and pulse position modulation (PPM) can be used to provide self‐synchronised data and clock for wireless implantable neural recoding systems, and therefore simplifies the circuit architecture. Presented is a novel ultra‐low‐power clock and data recovery (CDR) circuit based on ASK‐PPM. The CDR includes a 1 MHz gain‐boosted front‐end amplifier with an inductive load for ASK demodulation, and a charge‐bump based circuit to extract and recover clock and non‐return‐to‐zero (NRZ) data from the demodulated PPM signal. To increase the input data rate range that is able to be processed by this CDR, the reference voltage required for data recovery is adaptively generated, also from the PPM. The proposed design is fabricated in a standard CMOS 0.25 µm process. It exhibits an input sensitivity of − 13 dBm with 1 MHz input, covers an input data rate range between 19 and 76 kbit/s, and consumes only ∼ 100 µW of power.