Digital encoding calibrated unit used in 8 bit 1 GS/s folding and interpolating ADC. Issue 5 (1st March 2016)

• Record Type: Journal Article
• Authors: Wang, Linfeng; Meng, Qiao; He, Wenwei; Zhang, Daoyuan; Ma, Hengfei
• Is Part Of: Electronics letters. Volume 52:Issue 5(2016)
• Page Start: 344
• Page End: 346
• Publication Date: 2016-03-01
• Subjects: analogue‐digital conversion -- high‐speed integrated circuits -- CMOS integrated circuits -- comparators (circuits) -- encoding; digital encoding calibrated unit -- high‐speed folding ADC design -- interpolating ADC design -- coarse channel joint encoding technology -- comparator -- error encoding -- CMOS technology -- bit rate 8 Gbit/s; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.3934
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : In high‐speed folding and interpolating ADC design, an important issue is the encoding error result from the fine and coarse channel joint encoding technology. The last bit of the coarse channel only uses the last comparator of the fine channel to encode, the misjudgement of this comparator caused by offset and other non‐ideal factors will lead to the encoding error of the last bit of the coarse channel and deteriorate the linearity. A digital encoding calibrated unit is presented. It utilises the lowest four comparators of the fine channel instead of one to calibrate error encoding of the comparator. An 8 bit 1 GS/s folding and interpolating ADC with this digital encoding calibrated unit is fabricated in 180 nm CMOS technology has been used to assess the validity of the calibration.