Low‐cost memory data scheduling method for reconfigurable FFT bit‐reversal circuits. Issue 3 (1st February 2015)

• Record Type: Journal Article
• Authors: Gao, Wei; Kwong, Sam; Sang, Hongshi
• Is Part Of: Electronics letters. Volume 51:Issue 3(2015)
• Page Start: 217
• Page End: 219
• Publication Date: 2015-02-01
• Subjects: fast Fourier transforms -- semiconductor storage; low‐cost memory data scheduling method -- reconfigurable bit‐reversal circuits -- N‐2‐depth single‐port memories -- fast Fourier transform -- single‐port memories -- read address generation methods -- write address generation methods -- continuous data reordering tasks -- bit‐reversal design -- flexible length FFT processor; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2014.3715
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A low‐cost memory data scheduling method based on two N /2‐depth single‐port memories is proposed for reconfigurable fast Fourier transform (FFT) bit‐reversed data reordering tasks. To make single‐port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit‐reversal circuits are designed for continuous data reordering tasks. The proposed bit‐reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit‐reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.