Hysteresis settling technique for CMOS comparators based on substrate voltage. Issue 1 (1st January 2013)

• Record Type: Journal Article
• Authors: Rodrigues, C.R.; Muller, C.; Neto, D.J. Monteiro
• Is Part Of: Electronics letters. Volume 49:Issue 1(2013)
• Page Start: 27
• Page End: 28
• Publication Date: 2013-01-01
• Subjects: voltage; CMOS analogue integrated circuits -- comparators (circuits) -- semiconductor switches; hysteresis settling technique -- substrate voltage -- CMOS comparators -- MOS differential comparator -- bulk‐source voltage -- input signal polarity -- rail voltage -- reference control voltage -- pMOS switches -- XFAB 0.35XH technology -- control rule -- voltage 0 mV to 500 mV; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2012.3191
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A hysteresis is a widely employed solution to mitigate the effect of noise on comparators. Presented is a very simple technique, applicable to any topology of MOS differential comparator. It consists of imposing different bulk‐source voltage to the input MOS differential pair. Depending on the polarity of the input signal, one substrate is connected to the rail voltage and the other to a reference control voltage. So, when the slope inverts the connections are switched through pMOS switches. Simulation results show that the hysteresis up to 302, 6 mV can be linearly controlled for bulk voltages ranging from 0 to 500 mV, for XFAB 0.35XH technology. Finally, an aproximation for the control rule is proposed.