Cite
HARVARD Citation
Yu, X. et al. (2013). 0.6mW 6.3 GHz 40nm CMOS divide‐by‐2/3 prescaler using heterodyne phase‐locking technique. Electronics letters. 49 (7), pp. 471-472. [Online].
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Yu, X. et al. (2013). 0.6mW 6.3 GHz 40nm CMOS divide‐by‐2/3 prescaler using heterodyne phase‐locking technique. Electronics letters. 49 (7), pp. 471-472. [Online].