0.6mW 6.3 GHz 40nm CMOS divide‐by‐2/3 prescaler using heterodyne phase‐locking technique. Issue 7 (1st March 2013) - Yu, X.P.; Lu, Z.H.; Lim, W.M.; Yeo, K.S.
Abstract : A dual‐modulus prescaler based on the heterodyne phase‐locking technique is presented. Different to the conventional LC tank based phase‐locked loop, by directly locking at two injection‐locked ring oscillators simultaneously, a dual‐modulus operation is achieved while a wide‐range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide‐by‐2 and 3 dual‐modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.