A 21.5 25 GHz 7‐bit phase shifter with passive vector‐sum topology. Issue 6 (23rd January 2021) - Wu, Tianjun; Zhang, Xiaoning; Xing, Zhao; Zhao, Chenxi; Yu, Yiming; Liu, Huihua
Abstract: A 7‐bit passive phase shifter with low‐phase error is presented in 65 nm CMOS technology. The vector‐sum topology is implemented to enable passive phase shifter the ability of flexible phase calibration. Therefore, the passive phase shifter with high resolution and low‐phase error is achieved. In order to achieve high linearity, attenuator based on resistor is implemented to scale the I/Q signals, and a vector synthesizer based on balun is utilized to sum the quadrature vectors. Measurement results show that the phase shifter achieves 7‐bit resolution. The measured root mean square (RMS) phase error is <2.1°, and the RMS gain error is <1.2 dB over 21.5 25 GHz. The measured input‐referred P1dB is >10 dBm. The measured peak gain is about −14.3 dB, and the return loss is >8 dB. The chip has no DC power consumption and occupies an area of 880 × 500 um. The measurement results demonstrate the proposed phase shifter is very suitable for high linearity and high‐angular resolution phased arrays in K‐band.