A new dual-network bootstrapped switch for high-speed high-resolution applications. (May 2021) - Sotoudeh, Mehdi; Rezaei, Farzan
Highlights: Using two parallel networks n and p with separate controllers. Reducing ON resistance and charge injection as result of using dual-network structure. Achieving high linearity and high resolution. SNDR improved by 20.43% and the THD by 20.54%, compared with the conventional switch. No need for clock booster circuit that results in less complexity and less cost. Abstract: This paper proposes a new dual-network bootstrapped switch, which can be used in high-speed high-resolution applications. In this switch, two parallel networks (NMOS and PMOS networks) are used to reduce the on-resistance (Ron ) and the charge injection of the sampling transistor and increase the proposed switch's linearity and resolution. Simulation results show that the proposed switch achieves signal to noise and distortion ratio (SNDR) of 100.45 dB and spurious-free dynamic range (SFDR) of 102.78 dB for a 10 MHz input voltage with an amplitude of 1.8 V peak-to-peak at 100 MHz sampling frequency. Furthermore, the Monte-Carlo simulations are performed in Cadence spectre, and the results show good performance of the proposed scheme in terms of linearity and resolution. Compared with the conventional switch, the proposed method increases the SNDR by 20.43% and the total harmonic distortion (THD) by 20.54%. Graphical abstract: Image, graphical abstract