Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates. (25th June 2020)

• Record Type: Journal Article
• Authors: Alamdar, Hani; Ardeshir, Gholamreza; Gholami, Mohammad
• Is Part Of: International journal of circuit theory and applications. Volume 49:Number 1(2021)
• Page Start: 196
• Page End: 212
• Publication Date: 2020-06-25
• Subjects: flip‐flop -- nand‐nor‐inverter -- NNI -- PFD -- phase‐frequency detector -- QCA -- quantum‐dot cellular automata; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2825
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm 2 area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm 2 occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates. Abstract : In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and a new inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm 2 area. The proposed PFD has 141 cells, 0.17‐μm 2 occupied area, and two clock cycle latency.