An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. (January 2021) - Vidhyadharan, Abhay S.; Vidhyadharan, Sanjay
Abstract: This paper presents an ultra-low-power ternary dynamic Half Adder (HA) design which consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as compared to the other designs reported in the literature. Conventional ternary circuit designs use single V DD power supply, which is not a power-efficient technique. In these designs, the intermediate ternary logic state ( V DD /2) is generated by allowing a steady-state current through two diode-connected transistors connected in series and the output is obtained from the junction of the two transistors. The proposed dual- V DD HA design utilizes both the available ternary power supply voltages ( V DD & V DD /2) and prevents direct path between the power supplies and ground, in all the three possible ternary logic output states, resulting in a significant reduction in power consumption. While Carbon Nanotube FETs (CNFETs) is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed dual- V DD ternary dynamic HA design has been implemented with both CNFET and 45 nm CMOS devices. The proposed CNFET HA has an average delay of merely 8.4 ps, which is lower than the delays experienced in conventional designs (16.5–60.5 ps). The overall decrease in Power Delay Product (PDP) is 72–98% in the proposed CNFET HA, with respect to the other designs reported in the literature.