Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. (April 2021)

• Record Type: Journal Article
• Authors: Wang, Jue; Cheng, Xu; Han, Jun; Zeng, Xiaoyang
• Is Part Of: Microelectronics journal. Volume 110(2021)
• Publication Date: 2021-04
• Subjects: Analog-to-digital converter (ADC) -- Phase detector -- Tri-level resistor digital-to-analog converter; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105007
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a synthesizable lead-lag quantization technique for all-digital delta sigma (ΔΣ) analog-to-digital converters (ADCs) based on voltage-controlled oscillator (VCO). Synthesizable circuitry is proposed to realize this technique, including a lead-lag phase detector (LLPD) and a tri-level resistor digital-to-analog converter (TRDAC) for feedback. It distinguishes the leading and lagging phases in an N-stage dual-VCO quantizer so that the resolution increases from log2 (N+1) bits to log2 (2 ​N ​+ ​1) bits. The TRDAC is also used as biasing DAC and suppresses the process variation. Taking the digital-like analog/mixed-signal design flow, the proposed ADC is implemented in 28-nm CMOS technology occupying only 0.0039 ​mm 2 . The simulation results show that it consumes 0.552 ​mW ​at a 0.9-V power supply, and achieves a 66.9-dB signal-to-noise-and-distortion ratio (SNDR) at 900 ​MS/s over 6-MHz bandwidth. With a similar SNDR to prior works, this technique lowers the Figure-of-Merit (FoM) to 25.5 fJ/conv.-step.