A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip. (12th October 2020)

• Record Type: Journal Article
• Authors: Alaei, Mohammad; Yazdanpanah, Fahimeh
• Is Part Of: Concurrency and computation. Volume 33:Number 6(2021)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-10-12
• Subjects: FPGA -- low‐power design -- multicrossbar -- network‐on‐chip -- priority‐based router; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.6055
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: High performance system‐on‐chip (SoCs) designs have led to high‐density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network‐on‐chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high‐performance FPGA‐based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low‐power NoC router with high performance in terms of energy‐efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA‐based NoC with mesh topology. Performance evaluations include network‐level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures.