Statistical gate-delay modeling with copulas. (January 2021)

• Record Type: Journal Article
• Authors: Schneider, Walter
• Is Part Of: Microelectronics journal. Volume 107(2020)
• Publication Date: 2021-01
• Subjects: Statistical gate-delay -- Process variations -- Copulas; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104938
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.