A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock. (January 2021)

• Record Type: Journal Article
• Authors: Verducci, Sir Orlando; Oliveira, Duarte L.; Batista, Gracieth C.; Curtinhas, Tiago S.
• Is Part Of: Microelectronics journal. Volume 107(2020)
• Publication Date: 2021-01
• Subjects: Genetic algorithm in partitioning -- Low-power state assignment -- SET-Flip-flops -- DET-Data-path; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104947
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The continuous search for higher performances and low power dissipation on digital systems shows to be critical. The pipeline control is a good alternative for achieving good results, but the activity of the clock is responsible for the high consumption of 15–45% of the total circuit energy. Decreasing the clock activity leads not only to a reduction of this consumption but also to a reduction of noise and electromagnetic interference. An interesting approach to achieve this goal is the design of synchronous digital systems that operate in both edges of the clock signal (double-edge triggered – DET), allowing a reduction of 50% in the operating frequency while maintains the same data processing rate. As we know, the use of double-edge triggered flip-flops (DET-FF) leads to some main drawbacks. Then, in this paper, we propose a novel method that allows synthesizing synchronous digital systems with pipeline control. Such control operates in both edges of the clock using only standards flip-flops (single-edge triggered flip-flops-SET-FF) as components of the state memories. The method was validated for a well-known example (second order differential equation solver), and it was applied to a set of 5 well-known benchmarks, showing a mean reduction of 53% in latency time when compared to conventional methods working at the same frequency (in the case 50MHZ). We achieved an average reduction of 10% in latency time when the operating frequency of our projects was reduced to 25MHZ and compared to conventional ones at 50MHZ. The proposed method leads to a mean reduction of 45% in dynamic power consumption when compared to conventional ones. These results, although presenting a minimum area penalty, show a high potential of practical implementations focusing on low-power and high performances. Graphical abstract: Image 1 Highlights: An architecture for digital systems to operate on DET_clock. An approach integrating partitioning and SET-FFs for synthesis of FSMs with DET_clock. A low consumption architecture for FSMs integrating gated-clock and partitioning. Indication of low consumption states aimed at FSMs with DET_clock.