Design of CMOS three-stage amplifiers for near-to-minimum settling-time. (January 2021)

• Record Type: Journal Article
• Authors: Giustolisi, Gianluca; Palumbo, Gaetano
• Is Part Of: Microelectronics journal. Volume 107(2020)
• Publication Date: 2021-01
• Subjects: Settling-time -- Operational transconductance amplifiers -- Three-stage amplifiers -- Feedback amplifiers -- CMOS -- Low-voltage; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104939
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, we provide a new procedure that allows to design a generic three-stage amplifier from settling-time specifications. The procedure analyze the settling-time of pure two- or three-pole amplifiers (i.e., with no zeros) and extends the results to a generic amplifier that includes one or two zeros even placed in the right-half plane. The validity of the proposed approach is demonstrated through a design example of a three-stage CMOS amplifier suitable for switched-capacitor applications.