Implementation and validation of quadral-duty digital PWM to develop a cost-optimized ASIC for BLDC motor drive. (April 2021)

• Record Type: Journal Article
• Authors: Mishra, Pratikanta; Banerjee, Atanu; Ghosh, Mousam; Gogoi, Sushanta; Meher, Pramod Kumar
• Is Part Of: Control engineering practice. Volume 109(2021)
• Publication Date: 2021-04
• Subjects: Application-specific integrated circuit (ASIC) -- Brushless DC (BLDC) motor -- Digital pulse-width modulation (DPWM) -- Field-programmable gate array (FPGA); Automatic control -- Periodicals; 629.89
• DOI: 10.1016/j.conengprac.2021.104752
• Languages: English
• ISSNs: 0967-0661

Abstract

Abstract: In this paper, a quadral-duty digital pulse width modulation (QDPWM) technique-based low-cost hardware architecture for brushless DC (BLDC) motor drive is proposed. The proposed architecture is developed by incorporating an efficient speed calculation and commutation circuitry to achieve the compactness of the total architecture. The speed calculation circuit is designed to perform edge detection of the rotor position signal, with external noise and glitch resistance. The proposed architecture is implemented in the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platform using TSMC 180 nm technology library. The FPGA implementation is compared with existing architectures to validate the resource utilization of the proposed architecture. The ASIC implementation illustrates that the proposed architecture operating at 50 MHz, reduces the gate count and power dissipation to approximately half and one-third, respectively, compared to a standard PI controller based-PWM control architecture. Experimental validation of the FPGA-based architecture is also performed using a laboratory prototype of the BLDC motor drive hardware setup. The performance of the drive is examined for various speed commands and loading conditions. Extensive experimental analysis has been carried out to validate the performance of the proposed architecture-based drive under dynamic load and speed command variation. The ability of the proposed circuit to tolerate the noise in Hall position sensor signals is testified by adding intentional glitches into the signal. Highlights: Quadral-duty digital pulse width modulation (QDPWM) controller-based hardware architecture for BLDC motor drive is designed. A single Hall sensor-based speed calculation circuit incorporated in the IC is designed to be simple and noise-tolerant. Architecture is implemented in FPGA and ASIC platforms using TSMC 180 nm technology library. With the IC, the gate count is reduced to half and the power dissipation is decreased to only one third if compared to PI controller-based design at 50 Hz working frequency.