A Pathway to Thin GaAs Virtual Substrate on On‐Axis Si (001) with Ultralow Threading Dislocation Density. Issue 3 (14th August 2020)

• Record Type: Journal Article
• Authors: Shang, Chen; Selvidge, Jennifer; Hughes, Eamonn; Norman, Justin C.; Taylor, Aidan A.; Gossard, Arthur C.; Mukherjee, Kunal; Bowers, John E.
• Other Names: Hammar Mattias guestEditor.; Hallén Anders guestEditor.; Lourdudoss Sebastian guestEditor.
• Is Part Of: Physica status solidi. Volume 218:Issue 3(2021)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-08-14
• Subjects: heteroepitaxy -- molecular beam epitaxy -- on-axis Si -- silicon photonics -- threading dislocation reductions; Solid state physics -- Periodicals; Solids -- Industrial applications -- Periodicals; 530.41
• DOI: 10.1002/pssa.202000402
• Languages: English
• ISSNs: 1862-6300

Abstract

Abstract : With recent developments in high‐speed and high‐power electronics and Si‐based photonic integration, the concept of monolithic III–V/Si integration through epitaxial methods is gaining momentum. However, the performance and reliability of epitaxially grown devices are still limited by defects in the semiconductor material, especially the threading dislocation density (TDD). Herein, a novel "asymmetric step‐graded filter" structure grown by molecular beam epitaxy (MBE) is proposed based on a systematic study of the commonly used techniques for threading dislocation reduction for high‐quality GaAs on Si (001) growth. The proposed structure greatly enhances the plastic relaxation in the filter layers. A surface TDD lower than 2 × 10 6 cm −2 is achieved with a total buffer thickness of only 2.55 μm. This provides a clear pathway to further reduce defect density down to the theoretical limit in the 10 5 cm −2 regime with a thin buffer structure. Abstract : The proposed novel "asymmetric‐step‐graded" filter structure greatly promotes the degree of plastic relaxation in the dislocation filter layers. A record‐low defect density in GaAs grown on on‐axis Si (001) is achieved with thin buffer layers. This serves as the platform for the monolithic integration of silicon photonic devices with high reliability at elevated temperatures.