A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET. (February 2021) - Kaur, Sarabjeet; Raman, Ashish; Sarin, Rakesh Kumar
Abstract: In this paper, a charge-based capacitance model has been proposed for a double-gate (DG) hetero-gate-dielectric tunnel FET (HGD-TFET). By solving the Poisson equation, the surface potential model is developed. The developed potential model is then used for developing the terminal capacitance model and drain current model. The device is working under enhancement-mode as the channel region is considered to be n-type doped. For developing the charge model, accumulated charges and ionized impurity charges are included in the channel charge equation. The developed model can capture the impact of VG  = 0 V and VD  = 0 V. The model can also successfully capture the scaling issues and gate dielectric variation. To ensure the performance of the developed model, the results are validated with TCAD simulation results and a good agreement is achieved between them. Since, high-k gate dielectric and low-k gate dielectric are used in a single structure, it combines the merit of both and hence, results in the performance improvement. Highlights: Physics-based analytical model has been developed for Hetero-gate dielectric TFET. Surface potential, capacitance and drain current for HGD-TFET are modeled. The models include the impact of zero gate bias and zero drain bias. Impact of scaling and dielectric variation can also be captured by the developed model.