(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond. (18th August 2016)

• Record Type: Journal Article
• Authors: Andrieu, François; Berthelon, Remy; Morvan, Simeon; Gourhant, Olivier; Baylac, Elise; Le Royer, Cyrille; Dutartre, Didier; Josse, Emmanuel; Haond, Michel
• Is Part Of: ECS transactions. Volume 75:Number 8(2016)
• Page Start: 3
• Page End: 14
• Publication Date: 2016-08-18
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/07508.0003ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-performance at the 14nm node. At the same time, it induces strong layout effects, which are reported and explained in this paper. They can be reproduced by an accurate physics-based electrical model, which enables us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading experimentally to a -15 percent delay reduction for a ring-oscillator of 1-gate finger inverters at 0.8V supply voltage. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Namely, a continuous-RX design, which consists in a long active line configuration, optimizes the stress configuration, maintaining a high level of longitudinal compressive stress, while relaxing the transverse one. A 28 percent ring oscillator delay improvement is experimentally demonstrated at a given leakage for 1-finger inverter at 0.8V supply voltage. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. Finally, we discuss the technological knobs and especially the strain boosters that can furthers the scaling of FDSOI below the 14nm node: SiGe channel and source/drain of high-Ge content, influence of the surface orientation and channel direction, as well as the gate last integration.