Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability. (18th August 2016) - Mudgal, Tarun; Edwards, Nicholas; Ganesh, Prashant; Bharadwaj, Anish; Powell, Eli; Pierce, Michael S; Manley, Robert G.; Hirschman, Karl D
Abstract : This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance. Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Device operation and response to applied bias-stress of all three gate electrode configurations will be compared, with reference to TCAD simulations that utilize common bulk and interface defect models. Electrical measurements and TCAD simulations are also used to develop a hypothesis on the origin of non-ideal behavior observed on scaled devices, which can be addressed by appropriate gate electrode option.