(Invited) Interface Engineering of High-k Dielectrics and Metal Contacts for High Performance Top-Gated MoS2 FETs. (16th August 2017)

• Record Type: Journal Article
• Authors: Bhattacharjee, Shubhadeep; Ganapathi, K. L.; Mohan, Sangeneni; Bhat, Navakanta
• Is Part Of: ECS transactions. Volume 80:Number 1(2017)
• Page Start: 101
• Page End: 107
• Publication Date: 2017-08-16
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08001.0101ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : A combination of contact and gate dielectric engineering is utilized to achieve very high performance few layer MoS2 FET. Sulfur treatment before the formation of Ni and Pd source/drain contacts helps in reducing the schottky barrier height and thereby resulting in 10x reduction in contact resistance. The e-beam evaporated 30nm HfO2 gate dielectric, with optimized processing condition, yields 6.1nm EOT, with interface trap density in the mid 10 11 /cm 2 range. The top gated MoS2 FET demonstrates field effect mobility of 63 cm 2 /V-sec. This FET is used along with a depletion mode n-channel FET load, to demonstrate inverter circuit characteristics with output to input gain of 9.