The Impact of Dummy Gate Processing on Si-Cap-Free SiGe Passivation: A Physical Characterization Study on Strained SiGe 25% and 45%. (15th August 2017)

• Record Type: Journal Article
• Authors: Wostyn, Kurt; Ragnarsson, Lars-Åke; Schram, Tom; Witters, Liesbeth; Conard, Thierry; Douhard, Bastien; Vanhaeren, Danielle; Holsteyns, Frank; Vandervorst, Wilfried; Horiguchi, Naoto
• Is Part Of: ECS transactions. Volume 80:Number 2(2017)
• Page Start: 155
• Page End: 162
• Publication Date: 2017-08-15
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08002.0155ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : Si-cap-free SiGe passivation suffers from the potential presence of Ge-oxide in the interlayer prior to high-k deposition. Most of the advanced transistor designs use a replacement metal gate (RMG) integration scheme. The evolution of the Ge-content in the chemical oxide formed on SiGe channels with [Ge] = 25 and 45% was followed after the oxidation of pristine SiGe and compared to SiGe that was exposed to a short-loop flow mimicking an RMG integration scheme. The Ge content of the chemical oxide and SiGe virtual substrate was found to be strongly dependent on the spike anneal temperature. Also the roughness of the interlayer was found to increase. The impact of a TMAH-based clean prior to chemical oxide formation was also studied. Finally, the observations are explained qualitatively as a combination of the behavior for Si and Ge.