(Invited) Challenges to Implement Resistive Memory Cells in the CMOS BEOL. (17th August 2017)

• Record Type: Journal Article
• Authors: Al-Mamun, Mohammad; Orlowski, Marius K
• Is Part Of: ECS transactions. Volume 80:Number 6(2017)
• Page Start: 13
• Page End: 23
• Publication Date: 2017-08-17
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08006.0013ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : The paper reviews the manifold challenges of implementing resistive switching memory cell into back-end-of-line of CMOS. The challenges include not only the choice of materials of a stand-alone CBRAM cell, but also the way the cell is embedded in BEOL. In case of the inert electrode, a composite electrode is required with appropriate glue layer, heat transport layer, and inert metal proper with sufficient thermal conductivity, low miscibility with, and low surface diffusivity of the active metal atoms. The active metal is required to allow for a copious redox reaction but simultaneously to prevent reactions with the dielectric. A dielectric is preferred with a moderate level of defects which may be controlled by deposition processes. Finally, the choice of the materials is gated by the material and process compatibility with BEOL, as well as by the dynamics of resistive switching operations, including Joules heat during SET and RESET operations.