(Invited) Vertical Nanowire FET Integration and Device Aspects. (4th May 2016)

• Record Type: Journal Article
• Authors: Veloso, Anabela; Altamirano-Sánchez, Efraín; Brus, Stephan; Chan, B. T.; Cupak, Miroslav; Dehan, Morin; Delvaux, Christie; Devriendt, Katia; Eneman, Geert; Ercken, Monique; Huynh-Bao, Trong; Ivanov, Tsvetan; Matagne, Philippe; Merckling, Clement; Paraschiv, Vasile; Ramesh, Siva; Rosseel, Erik; Rynders, Luc; Sibaja-Hernandez, Arturo; Suhard, Samuel; Tao, Zheng; Vecchio, Emma; Waldron, Niamh; Yakimets, Dmitry; De Meyer, Kristin; Mocuta, Dan; Collaert, Nadine; Thean, Aaron
• Is Part Of: ECS transactions. Volume 72:Number 4(2016)
• Page Start: 31
• Page End: 42
• Publication Date: 2016-05-04
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/07204.0031ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin ), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.