Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology. (20th July 2018)

• Record Type: Journal Article
• Authors: Aydin, Ömür Işıl; Holt, Judson Robert; Le Royer, Cyrille; Vanamurthy, Laks; Feudel, Thomas; Heyne, Tobias; Gerber, Ralf; Lenski, Markus; Jansen, Sören; Utess, Dirk; Klein, Christoph; Peeva, Anita; Mulfinger, George Robert; McArdle, Timothy J; Barge, David; Divay, Alexis; Lehmann, Steffen; Smith, Elliot; Peters, Carsten; Sachse, Jens-Uwe
• Is Part Of: ECS transactions. Volume 86:Number 7(2018)
• Page Start: 199
• Page End: 206
• Publication Date: 2018-07-20
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08607.0199ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : Fully Depleted Silicon-On-Insulator (FDSOI) technology is a strong competitor in particular for RF applications, providing high performance at low manufacturing cost. In this technology, PFET devices utilize an epitaxially grown pFET raised source/drain (pRSD). However, the pRSD structure adds to the parasitic capacitance to the gate which is a detractor of RF performance. We demonstrate a faceted epitaxial RSD process that reduces this parasitic capacitance (CMiller ) by up to -25% and further improves the already high RF pFET fmax by +18%. In addition, we show improved defectivity (-80% non-selective growth defect count reduction), and reduced within-wafer CMiller variability (1-s reduced by -42%). All of these make faceted pRSD a powerful technique to significantly improve device performance in FDSOI.