Electrical Characterization of Dry and Wet Processed Interface Layer in Ge/High-K Devices. (8th September 2015)

• Record Type: Journal Article
• Authors: Ding, YI Ming; Misra, Durga; Bhuyian, Mdnasiruddin; Tapily, Kandabara; Clark, Robert D.; Consiglio, Steven; Wajda, Cory S.; Leusink, Gert J.
• Is Part Of: ECS transactions. Volume 69:Number 5(2015)
• Page Start: 313
• Page End: 322
• Publication Date: 2015-09-08
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/06905.0313ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : Even through Ge/high-k interface has been extensively studied, the high leakage current associated with these gate stacks and interface defects continue to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit and equivalent oxide thickness (EOT). In this work, the dry and wet processed interface layers for three different p type Ge/High-K samples on 300 mm wafers were studied at different low temperatures by CV and GV measurement. Since low temperature measurements are more reliable several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are reported and interface quality is being discussed.