Pseudo Split Gate In0.53Ga0.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis. (2nd November 2020) - Haris, Mohd; Loan, Sajad A.; Mainuddin,
Abstract: In this work, we present the design and simulation of a novel structure of In0.53 Ga0.43 As/InP based hetero junction tunnel field effect transistor (HTFET). The proposed HTFET employs two gates: the conventional main gate and a pseudo split gate (PSG) at the drain side. The PSG is placed at the top of the drain region with the same equivalent oxide thickness (EOT) and work function as that of the main gate at an optimized separation from gate electrode. The PSG is not an active gate and it is not connected to either VDD or gate voltage. Two dimensional simulation study has revealed that the proposed device suppresses ambipolar current by ~10 orders of magnitude as compared to a HTFET without overlap and by >7 orders as compared to overlapping gate on drain HTFET (OGD‐HTFET). The PSG‐based HTFET (PSG‐HTFET) also exhibits lesser total gate capacitance as compared to OGD TFET. The proposed PSG‐HTFET offers much better ambipolar suppression even at higher drain doping and lower EOT, as compared to OGD‐HTFET. Further, the PSG‐HTFET exhibits 50% and 40% lesser fall and rise propagation delays respectively as compared to the OGD‐HTEFT. Further, the voltage overshoot and undershoot have also been suppressed in the proposed PSG‐HTFET. The scalability analysis shows that the PSG‐HTFET has better scalability in terms of ambipolar suppression, total gate capacitance, and propagation delays.