Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices. (17th April 2015)

• Record Type: Journal Article
• Authors: Oba, Yoshiyuki; De Messemaeker, Joke; Tyrovouzi, Anna Maria; Miyamori, Yuichi; De Vos, Joeri; Wang, Teng; Beyer, Gerald; Beyne, Eric; De Wolf, Ingrid; Croes, Kristof
• Is Part Of: Japanese journal of applied physics. Volume 54:Number 5(2015:May)Supplement
• Publication Date: 2015-04-17
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.54.05EE01
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: Electromigration failure locations in three-dimensional (3D) interconnect structures with high-aspect-ratio through silicon vias, (TSVs, Φ5 × 50 µm 2 ) connected to 40-µm-pitch CuSn solder joints have been identified using test structures which were designed to avoid failures in the back-end-of-line (BEOL). The resistance of the structures with the TSV and bump connections showed a continuous increase until failure. For the structures without a bump connection, where only TSV and re-distributed line (RDL) were the electrically connected, the resistance remained constant prior to the final failure. From cross-sectional analyses after the test, the failure locations were identified at the TSV bottom or at the bump bottom. The location of void formation was changed by applied current direction. The flux divergence generated by the barrier metal and the reservoir effect plays a crucial role in the void formation, and each failure mode is considered to have a different impact on the reliability performance.