Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels. (30th April 2015)

• Record Type: Journal Article
• Authors: Tso, Chia-Tsung; Liu, Tung-Yu; Sheu, Jeng-Tzong
• Is Part Of: Japanese journal of applied physics. Volume 54:Number 6(2015:Jun.)Supplement 1
• Publication Date: 2015-04-30
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.54.06FG06
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13 mV/V), and a high I ON / I OFF current ratio (∼1 × 10 9 ) under a relatively low voltage condition ( V D = 0.3 V, V G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.