A single event upset hardened flip-flop design utilizing layout technique. (November 2019) - Wang, Haibin; Chu, Jiamin; Wei, Jinghe; Shi, Junwei; Sun, Hongwen; Han, Jianwei; Qian, Rong
Abstract: A novel Quatro-based flip-flop design with low penalty was proposed. By utilizing layout technique, SEU hardness was achieved in this design because of charge sharing between the introduced PMOS transistors. Both the proposed design and the reference flip-flop were fabricated in a 65 nm standard CMOS technology. The pulsed laser experiment results demonstrate that the new design has a larger upset threshold and lower SEU error rate compared with the reference. The area and delay penalties are not significant, i.e., 13% and 37%, respectively. Highlights: A single event upset resilient flip-flop design based on Quatro was proposed and tested in a 65 nm CMOS technology. Charge sharing is utilized to increase critical charge of the flip-flop. The area and delay penalties are insignificant compared with reference designs. Simulation and laser irradiation results confirm the effectiveness in reducing SEU susceptibility.