Low-Frequency Noise Assessment of Work Function Engineering Cap Layers in High-k Gate Stacks. (5th March 2019)

• Record Type: Journal Article
• Authors: Claeys, C.; Ritzenthaler, R.; Schram, T.; Arimura, H.; Horiguchi, N.; Simoen, E.
• Is Part Of: ECS journal of solid state science and technology. Volume 8:Number 2(2019)
• Page Start: N25
• Page End: N31
• Publication Date: 2019-03-05
• Subjects: Semiconductors - Silicon -- capping layers -- high-k dielectrics -- low frequency noise; Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2.0221902jss
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : Engineering the effective work function of scaled-down devices is commonly achieved by the implementation of capping layers in the gate stack. Typical cap layers are Al2 O3 for pMOSFETs and La-oxide or Mg for nMOSFETs. Besides introducing a dipole layer at the SiO2 /high-κ interface, the in-diffusion of the metal ions may lead to either passivation or generation of traps in the SiO2 /high-κ layer. This paper uses low frequency noise studies to determine the impact of capping layers on the quality of the SiO2 /HfO2 gate stacks. The influence on the trap profiles of different types of cap layers, different locations of the cap layer (below or on top of the HfO2 dielectric) and the impact of different thermal budgets, typically used for the fabrication of Dynamic Random Access Memory (DRAM) logic devices, are investigated. The differences between several metal oxides are outlined and discussed.